Emitter Function Logic (EFL) is a form of Current Mode Logic (CML) closely related to Emitter Coupled Logic (ECL). While EFL is not as well known as ECL, EFL has been known for several years, and several designs using EFL have been implemented. However, EFL has not been made commercially available as a logic family, although it has been shown to possess a distinct speed-power product advantage over ECL for some circuit configurations. One reason put forth for this relatively slow acceptance of EFL is the lack of both the true and complementary outputs from each gate as is customary with ECL circuits.
While some of the problems associated with the single output are simply ones of inconvenience, requiring a new design for some elementary functions, other problems are more formidable. An example of the latter problem is the design of a synchronous counter cell, which is advantageously implemented in the form of a D-type latch in conjunction with a D-type (read "D-bar type") latch.
As used herein, the term "latch" is taken as descriptive of a circuit which maintains at an output a binary state indefinitely, regardless of its data input, until enabled by a control signal to accept data at its data input and thereafter to maintain at the output a state indicative of the accepted data. A latch may be noninverting, e.g., D-type, meaning the output is the same logical state as the accepted data input, or inverting, e.g., D-type, indicating the output is the logical complement of the accepted data input.
While D-type latches are well known in EFL, D-type latches are not. One example of a D-type latch is described in U.S. Pat. No. 4,145,623 to R. L. Doucette and herein incorporated by reference. Doucette described an EFL D-type latch having both true and complementary outputs. However, a close examination indicates at least two drawbacks of the Doucette latch which are believed to adversely affect the switching speed of the latch.
First, as is known in the art, a principal speed limiting node of an EFL gate is the connection of the collector of the common base transistor, the pull-up resistor, and the base of the output emitter follower transistor (Q.sub.1, R.sub.1, Q.sub.2 in the Doucette patent). By connecting additional logic gates directly to this node, Doucette adds capacitance to this critical timing node and thereby adversely affects the switching speed of the gate.
Secondly, the addition of a second pull-up resistor to the collector of the output transistor (Q.sub.2 in Doucette) and the connection to the collector of an input transistor (Q.sub.5) to this collector junction produces a charge transfer on the collector to base capacitance of these two transistors equal to twice the logic voltage swing. Thus an original advantage of EFL, namely that of producing only a single logic voltage swing across the base to collector capacitance of the transistor, has been compromised.
Thus it can be appreciated that a D-type latch which switches with speeds comparable to a D-type latch is highly desirable. Also highly desirable are synchronous counters and counter cells which can be, but are not necessarily, implemented in EFL, in view of the speed-power advantages and other advantages which flow from the use of EFL.
Synchronous counters are typically realized with cascaded T flip-flops typically having, for BCD coding and/or for up/down count capability, explicit interconnecting combinatorial logic. For improvement in power-delay product and for other advantages, the structuring of counters without said logic is highly desirable. Furthermore, since flip-flops structured from D-type and/or D-type latches inherently have a superior power-delay product and other advantages over T flip-flops, the structuring of synchronous counters from said former flip-flops is also highly desirable.